A common component in many wireless communication devices is the phase locked loop (PLL). Typical applications of PLLs include, for example, FM de-modulators for use in radio transceivers and frequency synthesizers for wireless communications devices for a variety of communications protocols, for example Bluetooth.
Broadly, a PLL is a circuit utilising feedback in order to control the frequency of a generated signal. PLLs can be used to generate an output signal with a frequency that is a multiple of the frequency of a reference signal. The multiple could be an integer multiple. Alternatively, the multiple could be an irrational multiple. Another common use of PLLs is to generate a signal with a frequency that tracks changes in frequency of a reference signal. When a PLL tracks the frequency of the reference signal and outputs a signal with a frequency that is a known multiple of that reference frequency, the PLL is said to be “locked” onto the reference signal.
Typically, a PLL will contain some form of controllable oscillator responsive to an input signal and a phase detector for determining the phase difference between a reference signal and a signal generated from the oscillator. The phase detector will output a signal in dependence on the measured phase difference and this signal will be used to control the output of the oscillator. FIG. 1 shows a block diagram of an example PLL used to generate an output signal with a frequency which is an integer multiple of the frequency of a reference signal. In FIG. 1, a reference signal S0 of frequency F0 and a signal S2 of frequency F2 are input into a phase detector module 101. The phase detector module determines the phase difference between signals S0 and S2 and outputs an error signal in dependence on this difference into a low-pass filter (LPF) 102. The output signal of the Low-pass filter is a filtered error signal which is input into the control input of an oscillator 103. The oscillator outputs a signal S1 with a frequency F1 in dependence on the received input signal. The signal S1 is input into a divider module 104. The output signal of the divider is the signal S2, which is fed back into the phase detector module 101. If the phase difference between the reference signal and the output signal of the oscillator is held constant, or is zero, then the frequency of the output signal is fixed relative to the reference signal. This is known as phase-locking or frequency-locking.
Alternatively, a frequency detector can be used instead of a phase detector. A frequency detector outputs an error signal in dependence on the frequency difference between two input signals. If the frequency of the two input signals is equal (i.e., frequency locking has occurred), the frequency detector outputs a zero error signal. In contrast, a phase detector can output a finite, non-zero error signal when frequency locking has occurred.
Low pass filters (LPFs) such as LPF 102 in FIG. 1 are often used within PLLs to control the dynamics of the loop, such as, for example, how the loop responds to changes in the frequency of the input reference signal or changes at the divider. The cut-off frequency of the low-pass filter (i.e. the frequency of a signal where significant roll off starts to occur) affects what is known as the capture range. The capture range is defined as the band of frequencies over which the input signal frequency can vary and still cause the PLL to lock on from an unlocked state. Therefore in practice, it is often desirable to have a wide capture range so that lock-in can occur over a wide range of reference signal frequencies. The design of the low-pass filter is often a difficult task and depends on various factors. For example, if the cut-off frequency is too low the capture range will be decreased. However, a low cut-off frequency has the advantage that the PLL's response to input noise will be reduced and the response of the loop to sudden changes in input frequency (known as the transient response) will be damped.
A divider, such as divider 104 in FIG. 1, is used within a PLL to generate an output signal with a frequency which is a determined multiple of the reference signal frequency. The multiple could be a rational multiple or an irrational multiple depending on the type of divider. For a divider with a dividing factor N, the output frequency, F2 is related to the input frequency, F1, by the following equation:
                              F          2                =                              F            1                    N                                    (        1        )            
A simple description of the operation of a divider within a PLL now follows. An input signal S0 of frequency F0 is fed into a phase detector. The output signal from the phase detector is filtered and input into an oscillator which produces an output signal S1 with frequency F1. The signal S1 is input into the divider which produces a signal S2 with frequency F2, such that F2 is related to F1 by the equation F2=F1/N. The signals S2 and S0 are then input into the phase detector which produces an error signal dependent upon the value of the phase difference between the two signals. Frequency is the time derivative of phase; therefore zero frequency difference between signals S2 and S0 corresponds to a constant phase difference, not necessarily equal to zero. If the phase detector measures a constant phase difference then the frequencies of the two input signals must be equal, that is, F0=F2. Since the frequency of the output signal S1 of the oscillator is related to the frequency of the signal S2 by the equation F1=F2N, the output signal of the oscillator is related to the input reference signal S0 by the equation:F1=F0N  (2)
I.e., the effect of a divider within a PLL is to produce an output signal which has a frequency which is a defined multiple of the frequency of the input reference signal.
PLLs can be implemented in either digital or analogue circuitry. An analogue PLL circuit typically utilises an analogue phase detector and a voltage controlled oscillator (VCO). A VCO is an electronic oscillator that generates an output signal with a frequency that may be varied by an applied DC voltage. The VCO has a gain, Kv expressed in units of Hz/V. The output frequency Fout of a VCO can be expressed in terms of the gain Kv as:Fout=Fc+Kv(Vin)  (3)
Here Vin is the applied voltage to the VCO and Fc is the VCO offset frequency.
A PLL with a digital phase detector is known as a digital PLL (DPLL). A DPLL may still implement a VCO as in an analogue PLL, but may employ digital phase detectors. In a typical digital phase detector the input signals are converted to digital level square waves and a counter is configured to increment a known amount at the passing of a rising edge of the input reference signal and decrement a possibly different known amount at the passing of a rising edge of the second input signal. The output of the counter, possibly after additional filtering, can drive a digital to analogue converter (DAC), and the output signal of the DAC could suitably be proportional to the integral of the phase difference between the two input signals. For example, the output of the counter could be input into a DAC, and the input or output of the DAC could be low-passed filtered.
In practical implementations of electronic circuits it is nearly always desirable to reduce the physical size of the circuit. The continued reduction in size of transistors and digital logic gates for use in integrated circuits has led to a drastic reduction in the size of digital circuits. A smaller circuit occupies a smaller amount of area on a chip and is hence cheaper to produce. Analogue circuits, on the other hand, do not scale down as effectively as components decrease in size which can lead to problems in integrating analogue and digital components on a single integrated circuit.
Problems arising from the integration of analogue and digital components onto a single integrated circuit include, for example, the non-linear relationship between the voltage and the oscillator frequency exhibited by a sub-micron VCO, and the coupling of digital noise to the noise-sensitive analogue components through the substrate. In addition, VCOs are susceptible to producing unwanted noise. This is because any noise present in an input signal will be amplified by the gain Kv of the VCO and will translate into phase noise. To keep the phase noise at a minimum, it is therefore necessary to keep the gain Kv as low as possible. However, it can be seen with reference to equation (3) that a large gain is required in order for the VCO to operate over a wide tuning range. Typically, these design conflicts are overcome by implementing multiple digitally selectable capture ranges, where a suitable capture range is selected using a selection mechanism. The use of a VCO on an integrated circuit therefore requires a large design effort to operate effectively and does not benefit from the continued reduction in size of digital components.
There is thus a need for improved integration between analogue and digital components for use within a PLL.